High speed image sensors have been widely used in many applications in different fields including the automotive field, the machine vision field, and the field of professional video photography. The technology used to manufacture image sensors, and in particular, complementary-metal-oxide-semiconductor (CMOS) image sensors, has continued to advance at great pace. For example, the demand of higher frame rates and lower power consumption has encouraged the further miniaturization and integration of these image sensors.
One way to increase the frame rate of a CMOS image sensor may be to increase the number of readout circuits operating in parallel. In conventional image sensors, one column of pixels in a pixel array may share one readout circuit. In other examples of the conventional art, one column of pixel cells in a pixel array may share a plurality of readout circuits. These solutions provide a higher frame rate, but require more silicon area, which is not be helpful in the miniaturization of silicon image sensors.
In order to miniaturize the image sensors, stacked chips were implemented where the pixel sensor layer is stacked on a circuit layer and sub-portions of the circuit layer process the image data for the pixels directly above it. While this enables high efficiency super high speed image sensors, these stacked chip implementations suffer from block noise at the boundary of each of the sub-portions of the circuit layer. As a result, a moving object's image captured using this stacked chip implementation is distorted at the boundary of the sub-portions of the circuit layer while the handshake between each of the sub-portions of the circuit layer during the image processing also causes distortions. Analog-to-digital conversion (ADC) variations may also be seen at the boundary between each of the sub-portions of the circuit layer. Further, given that the pixel signal lines are also separated at the boundary, the pixel output may also visibly vary at the boundary.
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